COA100% Active LaboratorySIMULATION
5-Stage RISC Pipeline Hazard & Forwarding Unit Laboratory
Cycle-by-cycle clock execution grid across IF, ID, EX, MEM, WB pipeline stages. Visualizes Read-After-Write (RAW) data hazards, forwarding bypass multiplexers, and load-use stall bubbles.
COA • SIMULATION5-Stage RISC Pipeline Hazard & Forwarding Unit Laboratory
COA • CPU ARCHITECTURE5-Stage Classic RISC
5-Stage Pipeline Hazard & Forwarding Unit Laboratory
CLOCK CYCLE:T1of 12
Space-Time Pipeline Execution MatrixVertical: Instructions | Horizontal: Clock Cycles
| Instruction | T1 | T2 | T3 | T4 | T5 | T6 | T7 | T8 | T9 | T10 | T11 | T12 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD R1, R2, R3IF | IF | ID | EX | MEM | WB | · | · | · | · | · | · | · |
SUB R4, R1, R5 | · | IF | ID | EX | MEM | WB | · | · | · | · | · | · |
AND R6, R1, R7 | · | · | IF | STALL | ID | EX | MEM | WB | · | · | · | · |
OR R8, R4, R1 | · | · | · | IF | STALL | ID | EX | MEM | WB | · | · | · |
LW R9, 0(R8) | · | · | · | · | IF | ID | EX | MEM | WB | · | · | · |
ADD R10, R9, R2 | · | · | · | · | · | IF | ID | EX | MEM | WB | · | · |
StageIF
ADD R1, R2, R3
StageID
Idle / Bubble
StageEX
Idle / Bubble
StageMEM
Idle / Bubble
StageWB
Idle / Bubble
Hazard Analysis:
Forwarding Unit ACTIVE: Data hazards between consecutive ALU instructions (e.g. R1 written by ADD and read by SUB) are resolved without any stalls by forwarding the ALU output from EX/MEM latch directly into the ALU input multiplexer! Notice how instruction 6 (ADD R10, R9, R2) still requires 1 stall bubble because Load-Use hazard data is only ready after the MEM stage.
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