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Hardware Lab: 4-Step Fetch-Decode-Execute Micro-operation RTL
Inspect register transfer language (RTL) micro-operations across PC -> MAR, M[MAR] -> MBR, MBR -> IR, and PC + 1 increments during the basic instruction cycle.
COA • VISUALIZATIONAddressing Modes & Effective Address (EA) Visualizer
COA • CPU ARCHITECTUREOperand Fetch & Memory Dereference
Addressing Modes & Effective Address (EA) Visualizer
1. Instruction Opcode
LOAD R1, 8(R2)
Mode: INDEXED Addressing Mode
Base register plus index/offset value
2. Address Resolution Unit
DERIVATION FORMULA:
EA = [R2] + Displacement/Offset = 0x1004 + 0x0008 = 0x100C
Resolved EA: 0x100C
Memory Bus Accesses: 1 cycle(s)
3. Final Operand Fetched
0x7777 (MEM[0x100C])
Ideal for array and struct indexing (Array base address + index * element size).
CPU Internal Register FileWord-size: 16-bit
| R1 | 0x0000 | General Purpose |
| R2 | 0x1004 | General Purpose |
| PC | 0x0200 | Program Counter |
| XR | 0x0008 | Index Register |
RAM Physical Address SpaceWord Addressable
| 520 | 0x9999 | Memory Word |
| 4096 | 0x0042 | Memory Word |
| 4100 | 0x2000 | Memory Word |
| 4108 | 0x7777 | Memory Word |
| 8192 | 0x5555 | Memory Word |
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