Unit 1: Introduction to Organizations & Architecture 35 mins study timeINTERMEDIATE

Processor Organization, General Registers & Addressing Modes

Detailed study of CPU register sets, ALU bus interconnections, stack pointer mechanics, and fundamental addressing modes (Immediate, Direct, Indirect, Register Indirect, Indexed, Relative).

Verified: Faculty Peer Review Board

Learning Objectives

•Trace register state changes during instruction fetch and decode cycles.
•Differentiate between Zero-address, One-address, and Two-address machine architectures.
•Calculate Effective Addresses (EA) for all standard addressing modes.
•Implement and trace stack PUSH and POP pointer modifications in C.

Essential Prerequisites

•Basic memory concept and byte pointers
•Binary instruction opcode structure

🗣️ Hinglish Peer-Mentor Master Explanation

Processor Registers, Stack aur Addressing Modes ka Funda

Senior Peer Mentor • 100% Humanized

🗣️ Asli Funda (Conversational Breakdown):

Addressing mode ka matlab bas itna hai ki CPU instruction ko ye kaise pata chalega ki operand (data) kahan rakha hua hai. Kya data seedhe instruction ke andar likha hai (Immediate mode)? Kya kisi register mein hai (Register mode)? Ya RAM ke kisi address pe chupa hua hai (Direct/Indirect mode)? Program Counter (PC), Accumulator (AC), aur Memory Address Register (MAR) sab milkar step-by-step memory se data nikaalte hain.

☕ Real-Life Relatable Analogy:

Imagine karo pizza delivery: Immediate mode = Pizza already tumhare haath mein hai. Direct mode = Delivery wale ko seedhe tumhara house number pata hai. Indirect mode = Delivery wala pehle tumhare guard ke paas jaata hai, guard diary khol kar tumhara flat number batata hai (Pointer to pointer).

📝 University Exam Scoring Funda:

Effective Address (EA) calculate karne ka numerical pakka aata hai! Bas ye table ratt lo: Immediate: No EA. Direct: EA = Address field. Indirect: EA = M[Address field]. Indexed: EA = Address + Index Register. Relative: EA = PC + Offset.

🎯 Tech Interviewer Trap / Gotcha:

Puchte hain: 'Why do we need Indexed addressing in modern OS?' Seedha bolo: 'Arrays aur data buffers ko loop mein access karne ke liye Indexed mode use hota hai, jahan base address fixed rehta hai aur index register loop ke counter ke saath increment hota hai.'

⚡ 1-Line Revision Rule:Addressing Mode = Data dhoondhne ka GPS navigation rule.

Layer 1: Intuition & Why It Matters

The Core Mental Model

“Addressing modes are simply different ways of answering the question: 'Where is my data?'. Immediate is like cash in your pocket. Direct is a friend's address on a sticky note. Indirect is a sticky note that tells you to open a safe to get the actual address.”

Why This Exists

Compilers convert high-level programming constructs (like array lookups `arr[i]`, pointer dereferencing `*ptr`, and local function calls) directly into specific CPU addressing modes. Understanding these modes is necessary to write optimized C/C++ systems code and understand assembly disassembly.

Beginner Foundation

When the processor executes an instruction like ADD, it needs operands. Does the instruction bring the number itself? Or does it tell the CPU which register or RAM address to check? The addressing mode defines the rule for locating the target number.

Micro Concepts Decomposition

MICRO CONCEPT 1Canonical Object

Internal Processor Organization & Register Sets

The CPU comprises Program Counter (PC), Instruction Register (IR), Memory Address Register (MAR), Memory Data Register (MDR), Accumulator (AC), and General Purpose Registers (R0-R7). Internal buses route data between registers and ALU multiplexers.

Key Takeaway: PC holds the address of next instruction; IR holds current instruction opcode; MAR holds memory address being accessed.

MICRO CONCEPT 2Canonical Object

Stack Organization: Register Stack vs Memory Stack

A Stack is a LIFO (Last-In-First-Out) storage structure managed by a Stack Pointer (SP). A Register Stack uses dedicated internal flip-flops with bounded depth; a Memory Stack reserves a partition of RAM where SP decrements on PUSH and increments on POP (in typical descending stack architectures).

Key Takeaway: PUSH: SP <- SP - 1, M[SP] <- Data. POP: Data <- M[SP], SP <- SP + 1 (for downward growing stacks).

MICRO CONCEPT 3Canonical Object

Immediate, Direct, and Indirect Addressing Modes

Immediate: Operand is part of instruction (EA = None, value = field). Direct: Effective Address (EA) = Address Field. Indirect: Address field points to memory location containing the effective address (EA = M[Address Field]), requiring two memory accesses.

Key Takeaway: Immediate requires 0 memory accesses for operand; Direct requires 1; Indirect requires 2 memory accesses.

MICRO CONCEPT 4Canonical Object

Displacement Addressing: Relative, Base-Register, and Indexed

Relative: EA = PC + Address Offset (used for conditional branch jumps). Base-Register: EA = Base Register + Offset (used for relocatable code in OS). Indexed: EA = Index Register + Offset (used for array traversal where index register increments in loops).

Key Takeaway: Effective Address computation: EA = Base/Index/PC register + Displacement field.

Layer 3 & 4: Formal Specification & Mechanism

Hardware State Machine Architecture

Effective Address (EA) Formulas: 1. Immediate: Operand = A (in instruction) 2. Direct: EA = A 3. Indirect: EA = M[A] 4. Register Direct: Operand = R 5. Register Indirect: EA = [R] 6. PC-Relative: EA = PC + A 7. Indexed: EA = XR + A 8. Base Register: EA = BR + A 9. Auto-increment: EA = [R], R <- R + 1.

Step-by-Step Execution of Indirect Addressing (ADD @500): 1. Fetch: IR <- M[PC], PC <- PC + 1. 2. Decode: Control Unit decodes opcode ADD with Indirect bit set. 3. Memory Access 1: MAR <- 500. Read memory. MDR receives pointer value, say 1200. Thus, EA = 1200. 4. Memory Access 2: MAR <- 1200. Read memory. MDR receives actual operand, say 42. 5. Execute: AC <- AC + MDR. Total memory references: 1 for instruction + 2 for operand = 3 memory cycles.

Layer 7: Interactive Laboratory

Interactive Simulator

COA • SIMULATION5-Stage RISC Pipeline Hazard & Forwarding Unit Laboratory

Launch Fullscreen Lab

COA • CPU ARCHITECTURE5-Stage Classic RISC

5-Stage Pipeline Hazard & Forwarding Unit Laboratory

Enable Data Forwarding (Bypass Unit)

CLOCK CYCLE:T1of 12

Space-Time Pipeline Execution MatrixVertical: Instructions | Horizontal: Clock Cycles

Instruction	T1	T2	T3	T4	T5	T6	T7	T8	T9	T10	T11	T12
ADD R1, R2, R3IF	IF	ID	EX	MEM	WB	·	·	·	·	·	·	·
SUB R4, R1, R5	·	IF	ID	EX	MEM	WB	·	·	·	·	·	·
AND R6, R1, R7	·	·	IF	STALL	ID	EX	MEM	WB	·	·	·	·
OR R8, R4, R1	·	·	·	IF	STALL	ID	EX	MEM	WB	·	·	·
LW R9, 0(R8)	·	·	·	·	IF	ID	EX	MEM	WB	·	·	·
ADD R10, R9, R2	·	·	·	·	·	IF	ID	EX	MEM	WB	·	·

StageIF

ADD R1, R2, R3

StageID

Idle / Bubble

StageEX

Idle / Bubble

StageMEM

Idle / Bubble

StageWB

Idle / Bubble

Hazard Analysis:

Forwarding Unit ACTIVE: Data hazards between consecutive ALU instructions (e.g. R1 written by ADD and read by SUB) are resolved without any stalls by forwarding the ALU output from EX/MEM latch directly into the ALU input multiplexer! Notice how instruction 6 (ADD R10, R9, R2) still requires 1 stall bubble because Load-Use hazard data is only ready after the MEM stage.

Layer 5: Step-by-Step Worked Numerical Example

End-to-End Execution Trace

Given: PC = 200, R1 = 400, Index Register XR = 100. Memory contents: M[200] = 'LOAD 500', M[500] = 800, M[600] = 950, M[700] = 1200. Compute Effective Address and loaded value for: a) Direct Mode (Address = 500) -> EA = 500, Value = 800. b) Indirect Mode (Address = 500) -> EA = M[500] = 800. c) Indexed Mode (Address = 500) -> EA = XR + 500 = 100 + 500 = 600, Value = 950. d) PC-Relative Mode (Address = 500) -> EA = PC + 500 = 200 + 500 = 700, Value = 1200.

Layer 6: Active Runtime CodeLab

Step-by-Step Code Execution (C)

AURXON Sandbox

AURXON Digital Engine

Font

main.cGlacier Light

Ln 1 • GCC 13

// C Demonstration of CPU Addressing Mode Effective Address (EA) Engine
#include <stdio.h>
 
typedef struct {
    int PC;
    int AC;
    int R1;
    int XR; // Index Register
    int RAM[1024];
} CPU;
 
int resolveOperand(CPU *cpu, int mode, int operandField) {
    switch (mode) {
        case 0: // Immediate
            printf("[Immediate Mode] Operand is direct value: %d\n", operandField);
            return operandField;
        case 1: // Direct
            printf("[Direct Mode] EA = %d, Loaded = %d\n", operandField, cpu->RAM[operandField]);
            return cpu->RAM[operandField];
        case 2: // Indirect
            {
                int ea = cpu->RAM[operandField];
                printf("[Indirect Mode] Pointer at %d -> EA = %d, Loaded = %d\n", operandField, ea, cpu->RAM[ea]);
                return cpu->RAM[ea];
            }
        case 3: // Indexed
            {
                int ea = cpu->XR + operandField;
                printf("[Indexed Mode] XR(%d) + %d -> EA = %d, Loaded = %d\n", cpu->XR, operandField, ea, cpu->RAM[ea]);
                return cpu->RAM[ea];
            }
        default:
            return 0;
    }
}
 
int main() {
    CPU cpu = { .PC = 100, .AC = 0, .R1 = 40, .XR = 20 };
    cpu.RAM[200] = 350;  // Direct target or pointer
    cpu.RAM[350] = 999;  // Target of indirect
    cpu.RAM[220] = 777;  // Target of indexed (XR=20 + 200)
 
    printf("--- Simulating Addressing Modes ---\n");
    resolveOperand(&cpu, 0, 200); // Immediate
    resolveOperand(&cpu, 1, 200); // Direct
    resolveOperand(&cpu, 2, 200); // Indirect
    resolveOperand(&cpu, 3, 200); // Indexed
    return 0;
}

// C Demonstration of CPU Addressing Mode Effective Address (EA) Engine
#include <stdio.h>

typedef struct {
    int PC;
    int AC;
    int R1;
    int XR; // Index Register
    int RAM[1024];
} CPU;

int resolveOperand(CPU *cpu, int mode, int operandField) {
    switch (mode) {
        case 0: // Immediate
            printf("[Immediate Mode] Operand is direct value: %d\n", operandField);
            return operandField;
        case 1: // Direct
            printf("[Direct Mode] EA = %d, Loaded = %d\n", operandField, cpu->RAM[operandField]);
            return cpu->RAM[operandField];
        case 2: // Indirect
            {
                int ea = cpu->RAM[operandField];
                printf("[Indirect Mode] Pointer at %d -> EA = %d, Loaded = %d\n", operandField, ea, cpu->RAM[ea]);
                return cpu->RAM[ea];
            }
        case 3: // Indexed
            {
                int ea = cpu->XR + operandField;
                printf("[Indexed Mode] XR(%d) + %d -> EA = %d, Loaded = %d\n", cpu->XR, operandField, ea, cpu->RAM[ea]);
                return cpu->RAM[ea];
            }
        default:
            return 0;
    }
}

int main() {
    CPU cpu = { .PC = 100, .AC = 0, .R1 = 40, .XR = 20 };
    cpu.RAM[200] = 350;  // Direct target or pointer
    cpu.RAM[350] = 999;  // Target of indirect
    cpu.RAM[220] = 777;  // Target of indexed (XR=20 + 200)

printf("--- Simulating Addressing Modes ---\n");
    resolveOperand(&cpu, 0, 200); // Immediate
    resolveOperand(&cpu, 1, 200); // Direct
    resolveOperand(&cpu, 2, 200); // Indirect
    resolveOperand(&cpu, 3, 200); // Indexed
    return 0;
}

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Interactive Terminal Shell

Sandbox Terminal Ready

Click Run Code or press Ctrl+Enter to compile and execute.

Common Student Pitfalls & Mistakes

Where Students Lose Marks

❌ Mistake: Assuming PC-Relative addressing uses the current instruction address.

✓ Correct Understanding: By the time the processor executes the instruction, the PC has already been incremented to point to the next sequential instruction.

Layer 8: Practice & Knowledge Verification

Active Assessment Quiz

No Practice Questions Configured

Questions for this topic are currently undergoing faculty review.

Academic Evaluation Preparation

Viva Examination & University Scoring Strategy

Standard Viva Examination Questions

Q1: Why does Indexed Addressing facilitate array handling in high-level programming languages?

Answer: Because the base address of the array can be loaded as the fixed offset in the instruction, while the index register (XR) can be incremented in a loop counter to visit subsequent elements without modifying instruction code.

How to Write High-Scoring University Exam Answers

Classify addressing modes into Data Addressing and Control Addressing. Formulate Effective Address equations for Immediate, Direct, Indirect, Register Indirect, Relative, and Indexed. Solve the numerical finding Effective Address and Operand value with a given memory layout.