Unit 3: Control Units 40 mins study timeADVANCED

RISC vs CISC, Instruction Pipelining, Hazards & RAID Storage

Comparative analysis of RISC vs CISC design paradigms, 5-stage instruction pipeline (IF, ID, EX, MEM, WB), structural/data/control hazards, branch prediction, and RAID disk levels (0, 1, 5, 6, 10).

Verified: Faculty Peer Review Board

Learning Objectives

•Contrast RISC and CISC design metrics regarding instruction cycle count and compiler complexity.
•Calculate theoretical and actual pipeline speedup given stall cycles.
•Identify RAW, WAR, and WAW data hazards and trace hardware operand forwarding solutions.
•Evaluate RAID 0, 1, 5, and 6 storage configurations for high-availability database servers.

Essential Prerequisites

•Instruction execution cycles
•Registers and memory bus transfers

🗣️ Hinglish Peer-Mentor Master Explanation

Instruction Pipelining aur Hazards (RAW Data Hazard) ka Reality Check

Senior Peer Mentor • 100% Humanized

🗣️ Asli Funda (Conversational Breakdown):

Pipelining ka simple funda hai: Ek instruction khatam hone ka wait mat karo! Jab pehli instruction Execute stage mein ho, toh doosri ko Decode stage mein daal do, aur teesri ko Fetch stage mein. 5-Stage RISC pipeline: IF (Instruction Fetch), ID (Instruction Decode), EX (Execute), MEM (Memory Access), WB (Write Back). Lekin dikkat tab aati hai jab Instruction 2 ko wo data chahiye jo Instruction 1 abhi tak calculate hi kar rahi hai (Data Hazard). Isko solve karne ke liye CPU mein 'Hardware Forwarding Unit' hota hai jo result ALU se seedhe doosri instruction ko bypass karke de deta hai.

☕ Real-Life Relatable Analogy:

Laundromat (Kapde dhona): 4 steps hain - Washer (30 min), Dryer (30 min), Fold (30 min), Wardrobe (30 min). Agar tum pehle batch ke poore kapde wardrobe mein rakhne ke baad doosra batch daaloge toh 8 ghante lagenge. Smart banda kya karega? Jab pehla batch Dryer mein gaya, usi waqt doosra batch Washer mein daal dega!

📝 University Exam Scoring Funda:

Hazards 3 types ke hote hain: 1. Structural Hazard (Hardware resource collision), 2. Data Hazard (RAW, WAR, WAW), 3. Control Hazard (Branching aur jump instructions). Solution: Forwarding (Bypassing), Branch Prediction, aur NOP / Stall Bubbles.

🎯 Tech Interviewer Trap / Gotcha:

Read-After-Write (RAW) hazard kya hota hai? 'Jab instruction J ko kisi register ka value read karna ho jo instruction I abhi calculate karke write back nahi kar paayi hai. Agar forwarding na ho, toh pipeline ko 2 clock cycle ke liye stall/bubble lagana padega.'

⚡ 1-Line Revision Rule:Pipelining = Assembly line concurrency. Forwarding = Stall ko khatam karne wala internal hardware bypass.

Layer 1: Intuition & Why It Matters

The Core Mental Model

“Pipelining is like an industrial laundry service. Instead of washing, drying, folding, and ironing one person's clothes from start to finish before touching the next pile, you put load 2 in the washer while load 1 is in the dryer. Everyone gets clean clothes much faster.”

Why This Exists

Without pipelining, modern microprocessors would run 4x to 8x slower. Without RAID, enterprise cloud servers would lose petabytes of user data on inevitable hard drive mechanical failures. Both concepts represent the pinnacle of parallel engineering in computer systems.

Beginner Foundation

If doing 1 instruction takes 5 steps, executing 100 instructions normally takes 500 ticks. With pipelining, step 1 finishes, step 2 starts, while the next instruction begins step 1 immediately. After the pipe fills, one whole instruction finishes every single clock tick!

Micro Concepts Decomposition

MICRO CONCEPT 1Canonical Object

RISC vs CISC Architecture Philosophy

CISC (e.g. x86) emphasizes rich, complex multi-clock instructions, variable-length formats, and memory-to-memory operations. RISC (e.g. ARM, RISC-V) emphasizes simple single-cycle instructions, fixed-length formats, large register files, and strict load/store architecture.

Key Takeaway: RISC simplifies hardware to enable deep pipelining and high clock frequencies; CISC reduces program code size.

MICRO CONCEPT 2Canonical Object

The Classic 5-Stage Instruction Pipeline

Pipelining overlaps instruction execution across five stages: 1) IF: Instruction Fetch. 2) ID: Instruction Decode & Register Fetch. 3) EX: Execution / Effective Address calculation. 4) MEM: Memory access. 5) WB: Write Back result to register. Ideal speedup equals number of stages k.

Key Takeaway: Speedup = (k * n) / (k + n - 1), approaching k for large n instruction streams.

MICRO CONCEPT 3Canonical Object

Pipeline Hazards: Structural, Data, and Control

Structural: hardware resource conflict (e.g. single-port RAM accessed for IF and MEM simultaneously). Data (RAW - Read After Write): instruction depends on result not yet written back. Control: conditional branch redirects PC, forcing pipeline flush.

Key Takeaway: Resolved via: hardware stalls (bubbles), data forwarding (bypassing), branch prediction, and delayed branches.

MICRO CONCEPT 4Canonical Object

RAID Storage Architectures (Redundant Array of Independent Disks)

RAID 0: Block striping (max performance, 0 redundancy). RAID 1: Mirroring (100% redundancy, 50% capacity). RAID 5: Block striping with distributed parity (tolerates 1 disk loss, capacity = N-1). RAID 6: Dual parity (tolerates 2 disk losses). RAID 10: Striped mirrors.

Key Takeaway: RAID trades off capacity, write latency (parity calculation), and fault tolerance across physical storage arrays.

Layer 3 & 4: Formal Specification & Mechanism

Hardware State Machine Architecture

Pipeline Speedup Equation: Time non-pipelined = n * k * clock_cycle. Time pipelined = (k + n - 1) * clock_cycle + (stalls * clock_cycle). Data Hazard Classification: 1. RAW (True dependency): Inst J tries to read register before Inst I writes it. 2. WAR (Anti-dependency): Inst J tries to write register before Inst I reads it. 3. WAW (Output dependency): Inst J tries to write register before Inst I writes it. In standard in-order 5-stage pipelines, only RAW hazards occur naturally.

Resolving RAW Hazard with Operand Forwarding (ALU Bypass): Instruction 1: ADD R1, R2, R3 (R1 ready at end of EX stage cycle 3, written to register file in WB cycle 5). Instruction 2: SUB R4, R1, R5 (needs R1 at start of EX stage cycle 4). Without Forwarding: Pipeline must insert 2 stall bubbles. With Forwarding: Forwarding multiplexer routes EX/MEM pipeline register output directly into ALU input for cycle 4, achieving 0 stall bubbles!

Layer 7: Interactive Laboratory

Interactive Simulator

COA • SIMULATION5-Stage RISC Pipeline Hazard & Forwarding Unit Laboratory

Launch Fullscreen Lab

COA • CPU ARCHITECTURE5-Stage Classic RISC

5-Stage Pipeline Hazard & Forwarding Unit Laboratory

Enable Data Forwarding (Bypass Unit)

CLOCK CYCLE:T1of 12

Space-Time Pipeline Execution MatrixVertical: Instructions | Horizontal: Clock Cycles

Instruction	T1	T2	T3	T4	T5	T6	T7	T8	T9	T10	T11	T12
ADD R1, R2, R3IF	IF	ID	EX	MEM	WB	·	·	·	·	·	·	·
SUB R4, R1, R5	·	IF	ID	EX	MEM	WB	·	·	·	·	·	·
AND R6, R1, R7	·	·	IF	STALL	ID	EX	MEM	WB	·	·	·	·
OR R8, R4, R1	·	·	·	IF	STALL	ID	EX	MEM	WB	·	·	·
LW R9, 0(R8)	·	·	·	·	IF	ID	EX	MEM	WB	·	·	·
ADD R10, R9, R2	·	·	·	·	·	IF	ID	EX	MEM	WB	·	·

StageIF

ADD R1, R2, R3

StageID

Idle / Bubble

StageEX

Idle / Bubble

StageMEM

Idle / Bubble

StageWB

Idle / Bubble

Hazard Analysis:

Forwarding Unit ACTIVE: Data hazards between consecutive ALU instructions (e.g. R1 written by ADD and read by SUB) are resolved without any stalls by forwarding the ALU output from EX/MEM latch directly into the ALU input multiplexer! Notice how instruction 6 (ADD R10, R9, R2) still requires 1 stall bubble because Load-Use hazard data is only ready after the MEM stage.

Layer 5: Step-by-Step Worked Numerical Example

End-to-End Execution Trace

Problem: An unpipelined processor has a cycle time of 10 ns. A 5-stage pipelined version has a cycle time of 2.5 ns. For a program with 1,000 instructions where branch hazards cause 50 stall cycles, calculate the actual speedup. Solution: Non-pipelined time = 1000 * 10 ns = 10,000 ns. Pipelined clock cycles = (k + n - 1) + stalls = 5 + 999 + 50 = 1,054 cycles. Pipelined time = 1,054 * 2.5 ns = 2,635 ns. Speedup = 10,000 / 2,635 = 3.8x speedup.

Layer 6: Active Runtime CodeLab

Step-by-Step Code Execution (C)

AURXON Sandbox

AURXON Digital Engine

Font

main.cGlacier Light

Ln 1 • GCC 13

// C Simulation of 5-Stage Instruction Pipeline with Stall & Forwarding Logic
#include <stdio.h>
#include <stdbool.h>
 
typedef struct {
    int id;
    int destReg;
    int srcReg1;
    int srcReg2;
} Instruction;
 
void simulatePipeline(Instruction program[], int n) {
    printf("--- Simulating 5-Stage Pipeline Execution ---\n");
    int cycle = 0;
    int completed = 0;
 
    int lastDestInEX = -1;
    int lastDestInMEM = -1;
 
    for (int i = 0; i < n; i++) {
        cycle++;
        printf("Cycle %d: Fetching Inst %d (R%d = R%d op R%d)\n", cycle, program[i].id, program[i].destReg, program[i].srcReg1, program[i].srcReg2);
 
        // Check RAW Hazard against previous instruction
        if (i > 0 && (program[i].srcReg1 == program[i-1].destReg || program[i].srcReg2 == program[i-1].destReg)) {
            printf("  [RAW Hazard Detected] Inst %d depends on R%d from Inst %d\n", program[i].id, program[i-1].destReg, program[i-1].id);
            printf("  [Hardware Action] OPERAND FORWARDING engaged: bypassing EX/MEM latch! 0 stalls.\n");
        }
    }
    printf("Total Execution Cycles with Forwarding: %d (vs %d unpipelined)\n", cycle + 4, n * 5);
}
 
int main() {
    Instruction code[3] = {
        {1, 1, 2, 3}, // R1 = R2 + R3
        {2, 4, 1, 5}, // R4 = R1 - R5 (RAW on R1)
        {3, 6, 7, 8}  // R6 = R7 & R8
    };
    simulatePipeline(code, 3);
    return 0;
}

// C Simulation of 5-Stage Instruction Pipeline with Stall & Forwarding Logic
#include <stdio.h>
#include <stdbool.h>

typedef struct {
    int id;
    int destReg;
    int srcReg1;
    int srcReg2;
} Instruction;

void simulatePipeline(Instruction program[], int n) {
    printf("--- Simulating 5-Stage Pipeline Execution ---\n");
    int cycle = 0;
    int completed = 0;

int lastDestInEX = -1;
    int lastDestInMEM = -1;

for (int i = 0; i < n; i++) {
        cycle++;
        printf("Cycle %d: Fetching Inst %d (R%d = R%d op R%d)\n", cycle, program[i].id, program[i].destReg, program[i].srcReg1, program[i].srcReg2);

// Check RAW Hazard against previous instruction
        if (i > 0 && (program[i].srcReg1 == program[i-1].destReg || program[i].srcReg2 == program[i-1].destReg)) {
            printf("  [RAW Hazard Detected] Inst %d depends on R%d from Inst %d\n", program[i].id, program[i-1].destReg, program[i-1].id);
            printf("  [Hardware Action] OPERAND FORWARDING engaged: bypassing EX/MEM latch! 0 stalls.\n");
        }
    }
    printf("Total Execution Cycles with Forwarding: %d (vs %d unpipelined)\n", cycle + 4, n * 5);
}

int main() {
    Instruction code[3] = {
        {1, 1, 2, 3}, // R1 = R2 + R3
        {2, 4, 1, 5}, // R4 = R1 - R5 (RAW on R1)
        {3, 6, 7, 8}  // R6 = R7 & R8
    };
    simulatePipeline(code, 3);
    return 0;
}

1387 chars • 42 lines • Ln 1UTF-8 • 4 Spaces

Interactive Terminal Shell

Sandbox Terminal Ready

Click Run Code or press Ctrl+Enter to compile and execute.

⚡ AURXON Bitstream Runtime v4.8IDRAS Academic Virtual Node

Common Student Pitfalls & Mistakes

Where Students Lose Marks

❌ Mistake: Believing pipelining decreases the execution latency of a single instruction.

✓ Correct Understanding: Pipelining increases throughput (instructions completed per second), but slightly increases individual instruction latency due to pipeline latch register delays.

Layer 8: Practice & Knowledge Verification

Active Assessment Quiz

No Practice Questions Configured

Questions for this topic are currently undergoing faculty review.

Academic Evaluation Preparation

Viva Examination & University Scoring Strategy

Standard Viva Examination Questions

Q1: What is the difference between RAID 5 and RAID 6?

Answer: RAID 5 uses single distributed parity and can survive exactly 1 disk failure. RAID 6 uses dual distributed parity (Reed-Solomon / P+Q syndromes) and can survive up to 2 simultaneous disk failures.

Q2: How does data forwarding resolve RAW pipeline hazards?

Answer: By tapping the intermediate pipeline registers (EX/MEM or MEM/WB) and routing the calculated result directly into the ALU input multiplexer, bypassing the slow write-and-read through the register file.

How to Write High-Scoring University Exam Answers

Differentiate RISC and CISC across 6 criteria. Draw the space-time diagram for a 5-stage pipeline. Classify Structural, Data, and Control hazards with example code segments. Explain RAID 0, 1, 5, and 10 with parity layout sketches.