Unit 3: Control Units 30 mins study timeINTERMEDIATE

Instruction Formats, Cycles & Micro-Operation Sequences

Comprehensive breakdown of instruction word formats, register transfer language (RTL), fetch-decode-execute phases, control signals, and complete machine instruction execution.

Verified: Faculty Peer Review Board

Learning Objectives

•Formulate RTL micro-operation sequences for Fetch, Decode, and Execution of memory-reference instructions.
•Compare 3-Address, 2-Address, 1-Address, and 0-Address machine code implementations of arithmetic expressions.
•Construct timing state diagrams showing how sequence counters synchronize register transfers.

Essential Prerequisites

•Processor registers (PC, IR, MAR, MDR, AC)
•Memory bus timing concepts

🗣️ Hinglish Peer-Mentor Master Explanation

Instruction Cycle - Fetch, Decode, Execute ka Complete Lifecyle

Senior Peer Mentor • 100% Humanized

🗣️ Asli Funda (Conversational Breakdown):

CPU ki poori zindagi bas ek loop mein chalti hai: Instruction lao (Fetch), samjho kya karna hai (Decode), aur task perform karo (Execute). Har ek badi instruction chhote-chhote nano-seconds ke register transfers mein toot-ti hai jinko hum 'Micro-operations' kehte hain. Control unit ek orchestra conductor ki tarah timing signals (T0, T1, T2...) bhejta hai jo circuits ko enable karte hain.

☕ Real-Life Relatable Analogy:

Chef ki kitchen: Fetch = Recipe book se order padhna. Decode = Ingredients identify karna ki katori mein kya chahiye. Execute = Gas on karke frying pan mein cook karna. Store = Dish plate mein serve karna.

📝 University Exam Scoring Funda:

Register Transfer Language (RTL) mein Fetch cycle pakka likhne ko aata hai: T0: AR <- PC, T1: IR <- M[AR], PC <- PC + 1, T2: Decode opcode in IR, AR <- IR(0-11). Ye 3 lines likhte hi professor impress ho jaayenge!

🎯 Tech Interviewer Trap / Gotcha:

Hardwired Control Unit vs Microprogrammed Control Unit ka difference? Hardwired = Combinational logic gates se bana hota hai, superfast hota hai lekin RISC instructions badalna impossible hai. Microprogrammed = Control memory (ROM) mein micro-instructions store hoti hain, flexible hota hai lekin thoda slow hota hai.

⚡ 1-Line Revision Rule:Fetch (T0, T1) -> Decode (T2) -> Execute (T3-T6). Har instruction RTL steps mein execute hoti hai.

Layer 1: Intuition & Why It Matters

The Core Mental Model

“Think of an instruction as a musical score and the Control Unit as the conductor. The conductor taps the baton once per clock beat: on beat 1, the violinist turns the page; on beat 2, the cellist plays the note. Each individual action is an atomic micro-operation.”

Why This Exists

At the silicon level, the CPU is an orchestrated state machine. If micro-operations are out of order by even one nanosecond, register values become corrupted. Understanding RTL micro-operations reveals exactly how software instructions turn into electrical hardware signals.

Beginner Foundation

When your code says `x = a + b`, the CPU cannot do that in one flash. It must: 1) go fetch the command from RAM, 2) read what it means, 3) bring `a` from RAM, 4) bring `b` from RAM, 5) tell the adder to add them, and 6) store the answer. These tiny steps are micro-operations.

Micro Concepts Decomposition

MICRO CONCEPT 1Canonical Object

Instruction Fields and Word Formats

An instruction is divided into fields: Opcode (operation to perform, e.g. ADD), Addressing Mode specifier, and Operand Address fields. Based on address fields, machines are classified as 3-Address, 2-Address, 1-Address (Accumulator), or 0-Address (Stack).

Key Takeaway: Tradeoff: More address fields per instruction require longer instruction words but fewer total instructions to evaluate expressions.

MICRO CONCEPT 2Canonical Object

The Master Instruction Cycle: Fetch, Decode, Execute

Every machine instruction progresses through discrete sub-cycles: 1) Fetch: transfer instruction from memory to IR, increment PC. 2) Decode: determine opcode and operand locations. 3) Execute: manipulate ALU and registers. 4) Interrupt Check: verify external service requests.

Key Takeaway: Fetch and Decode micro-operations are identical for every instruction; Execute micro-operations vary based on decoded opcode.

MICRO CONCEPT 3Canonical Object

Register Transfer Language (RTL) Micro-Operations

Micro-operations are primitive atomic operations executed during one clock period. Fetch phase in RTL: T0: MAR <- PC; T1: MDR <- M[MAR], PC <- PC + 1; T2: IR <- MDR. Timing signals T0, T1, T2 ensure non-conflicting bus transfers.

Key Takeaway: A macro-instruction is broken down into a chronological sequence of clock-synchronized RTL micro-operations.

Layer 3 & 4: Formal Specification & Mechanism

Hardware State Machine Architecture

Detailed RTL breakdown for memory instruction ADD X (AC <- AC + M[X]): Fetch: T0: MAR <- PC T1: MDR <- M[MAR], PC <- PC + 1 T2: IR <- MDR Decode: T3: Control Unit decodes IR opcode, MAR <- IR(Address_field) Execute: T4: MDR <- M[MAR] T5: AC <- AC + MDR, Sequence Counter (SC) <- 0.

Evaluating X = (A + B) * (C + D) across architectures: 1. 3-Address: ADD R1, A, B; ADD R2, C, D; MUL X, R1, R2. (3 instructions) 2. 2-Address: MOV R1, A; ADD R1, B; MOV R2, C; ADD R2, D; MUL R1, R2; MOV X, R1. (6 instructions) 3. 1-Address (AC): LOAD A; ADD B; STORE T; LOAD C; ADD D; MUL T; STORE X. (7 instructions) 4. 0-Address (Stack): PUSH A; PUSH B; ADD; PUSH C; PUSH D; ADD; MUL; POP X. (8 instructions).

Layer 7: Interactive Laboratory

Interactive Simulator

COA • LABHardware Lab: 4-Step Fetch-Decode-Execute Micro-operation RTL

Launch Fullscreen Lab

COA • CPU ARCHITECTUREOperand Fetch & Memory Dereference

Addressing Modes & Effective Address (EA) Visualizer

1. Instruction Opcode

LOAD R1, 8(R2)

Mode: INDEXED Addressing Mode

Base register plus index/offset value

2. Address Resolution Unit

DERIVATION FORMULA:

EA = [R2] + Displacement/Offset = 0x1004 + 0x0008 = 0x100C

Resolved EA: 0x100C

Memory Bus Accesses: 1 cycle(s)

3. Final Operand Fetched

0x7777 (MEM[0x100C])

Ideal for array and struct indexing (Array base address + index * element size).

CPU Internal Register FileWord-size: 16-bit

R1	0x0000	General Purpose
R2	0x1004	General Purpose
PC	0x0200	Program Counter
XR	0x0008	Index Register

RAM Physical Address SpaceWord Addressable

520	0x9999	Memory Word
4096	0x0042	Memory Word
4100	0x2000	Memory Word
4108	0x7777	Memory Word
8192	0x5555	Memory Word

Layer 5: Step-by-Step Worked Numerical Example

End-to-End Execution Trace

Problem: Write the RTL micro-operations for instruction 'ISZ X' (Increment and Skip if Zero). Solution: T0: MAR <- PC T1: MDR <- M[MAR], PC <- PC + 1 T2: IR <- MDR, MAR <- IR(Address) T3: MDR <- M[MAR] T4: MDR <- MDR + 1 T5: M[MAR] <- MDR, if (MDR == 0) then (PC <- PC + 1), SC <- 0.

Layer 6: Active Runtime CodeLab

Step-by-Step Code Execution (C)

AURXON Sandbox

AURXON Digital Engine

Font

main.cGlacier Light

Ln 1 • GCC 13

// C Emulation of Instruction Fetch-Decode-Execute Micro-Operation Cycle
#include <stdio.h>
 
typedef struct {
    int PC, IR, MAR, MDR, AC;
    int RAM[256];
    int SC; // Sequence Counter
} SimpleCPU;
 
void runInstructionCycle(SimpleCPU *cpu) {
    printf("[T0] MAR <- PC (%d)\n", cpu->PC);
    cpu->MAR = cpu->PC;
 
    printf("[T1] MDR <- M[MAR] (%d), PC <- PC + 1\n", cpu->RAM[cpu->MAR]);
    cpu->MDR = cpu->RAM[cpu->MAR];
    cpu->PC++;
 
    printf("[T2] IR <- MDR (Opcode: %d)\n", cpu->MDR);
    cpu->IR = cpu->MDR;
 
    // Decode & Execute for ADD instruction (Opcode 1)
    if (cpu->IR == 1) { // ADD 50
        cpu->MAR = 50;
        printf("[T3] MAR <- Address Field (50)\n");
        cpu->MDR = cpu->RAM[cpu->MAR];
        printf("[T4] MDR <- M[50] (%d)\n", cpu->MDR);
        cpu->AC += cpu->MDR;
        printf("[T5] AC <- AC + MDR -> AC is now %d. Cycle complete.\n", cpu->AC);
    }
}
 
int main() {
    SimpleCPU cpu = { .PC = 0, .AC = 15 };
    cpu.RAM[0] = 1;  // Opcode 1 = ADD
    cpu.RAM[50] = 27; // Data at location 50
 
    runInstructionCycle(&cpu);
    return 0;
}

// C Emulation of Instruction Fetch-Decode-Execute Micro-Operation Cycle
#include <stdio.h>

typedef struct {
    int PC, IR, MAR, MDR, AC;
    int RAM[256];
    int SC; // Sequence Counter
} SimpleCPU;

void runInstructionCycle(SimpleCPU *cpu) {
    printf("[T0] MAR <- PC (%d)\n", cpu->PC);
    cpu->MAR = cpu->PC;

printf("[T1] MDR <- M[MAR] (%d), PC <- PC + 1\n", cpu->RAM[cpu->MAR]);
    cpu->MDR = cpu->RAM[cpu->MAR];
    cpu->PC++;

printf("[T2] IR <- MDR (Opcode: %d)\n", cpu->MDR);
    cpu->IR = cpu->MDR;

// Decode & Execute for ADD instruction (Opcode 1)
    if (cpu->IR == 1) { // ADD 50
        cpu->MAR = 50;
        printf("[T3] MAR <- Address Field (50)\n");
        cpu->MDR = cpu->RAM[cpu->MAR];
        printf("[T4] MDR <- M[50] (%d)\n", cpu->MDR);
        cpu->AC += cpu->MDR;
        printf("[T5] AC <- AC + MDR -> AC is now %d. Cycle complete.\n", cpu->AC);
    }
}

int main() {
    SimpleCPU cpu = { .PC = 0, .AC = 15 };
    cpu.RAM[0] = 1;  // Opcode 1 = ADD
    cpu.RAM[50] = 27; // Data at location 50

runInstructionCycle(&cpu);
    return 0;
}

1089 chars • 40 lines • Ln 1UTF-8 • 4 Spaces

Interactive Terminal Shell

Sandbox Terminal Ready

Click Run Code or press Ctrl+Enter to compile and execute.

⚡ AURXON Bitstream Runtime v4.8IDRAS Academic Virtual Node

Common Student Pitfalls & Mistakes

Where Students Lose Marks

❌ Mistake: Incrementing PC at the end of the instruction cycle instead of during Fetch T1.

✓ Correct Understanding: PC is incremented in T1 concurrently while waiting for memory read data, maximizing hardware utilization.

Layer 8: Practice & Knowledge Verification

Active Assessment Quiz

No Practice Questions Configured

Questions for this topic are currently undergoing faculty review.

Academic Evaluation Preparation

Viva Examination & University Scoring Strategy

Standard Viva Examination Questions

Q1: What is the difference between a micro-operation and a machine instruction?

Answer: A machine instruction (macro-instruction) is a binary code stored in memory specifying a complete operation (e.g. ADD). A micro-operation is an elementary, single-clock hardware register transfer that constitutes one sub-step of executing that instruction.

How to Write High-Scoring University Exam Answers

Define Instruction Cycle and list its phases. Write formal RTL micro-operations for Fetch, Decode, and Execution of ADD, LOAD, and BRANCH. Compare instruction formats based on number of address fields with code snippets.