Unit 5: Input/Output Devices and Microprocessors 35 mins study timeINTERMEDIATE

I/O Interface, Interrupts, DMA Controllers & Serial Communication

Programmed I/O vs Interrupt-driven I/O vs Direct Memory Access (DMA), DMA controller modes (Burst vs Cycle Stealing), vectored interrupt hardware, and synchronous/asynchronous UART communication.

Verified: Faculty Peer Review Board

Learning Objectives

•Compare Programmed I/O, Interrupt-Driven I/O, and DMA transfer rates.
•Draw the internal architecture of a DMA controller (Address, Word Count, Control registers).
•Trace the interrupt execution lifecycle including context saving and RETI instruction.
•List key 8051 SFRs (ACC, B, PSW, TMOD, TCON, SCON, IE, IP) and explain their memory mapping.

Essential Prerequisites

•System bus arbitration
•Stack PUSH and POP operations

🗣️ Hinglish Peer-Mentor Master Explanation

DMA Controller aur Interrupts - CPU ko bina disturb kiye Data Transfer

Senior Peer Mentor • 100% Humanized

🗣️ Asli Funda (Conversational Breakdown):

Agar CPU ko keyboard, mouse, sound card aur hard drive se ek-ek byte data khud manually copy karna pade, toh CPU ka 90% time sirf clerk ka kaam karne mein nikal jayega! Isliye hardware mein do super features hote hain: Interrupts aur Direct Memory Access (DMA). Interrupt ka matlab hai ki mouse ya network card CPU ko signal deta hai: 'Boss, mere paas data tayyar hai, jab free ho toh dekh lena'. Aur DMA Controller ek specialized chip hai jo high-speed devices (jaise SSD ya NIC) ka data seedhe RAM mein copy kar deti hai bina CPU ko pareshan kiye (Cycle Stealing ya Burst mode mein).

☕ Real-Life Relatable Analogy:

Restaurant mein waiter vs chef: Agar chef khud table pe jaakar order le aur bill banaye (Programmed I/O), toh khana kab banega? Chef kitchen mein cooking karta hai (CPU processing), aur dedicated waiters (DMA Controllers) samaan aur dishes serve karte rehte hain!

📝 University Exam Scoring Funda:

Programmed I/O vs Interrupt-Driven I/O vs DMA ka comparison chart pakka 7 ya 10 marks ka question hota hai! Cycle Stealing ka definition ratt lo: 'DMA controller CPU se bas 1 bus cycle chheen leta hai jab CPU internal ALU operations mein busy ho, taaki CPU execution zero delay pe chalta rahe.'

🎯 Tech Interviewer Trap / Gotcha:

Vectored Interrupt vs Non-Vectored Interrupt: 'Vectored Interrupt mein interrupting device khud bus par ek binary number (Vector Address) bhejti hai jo Interrupt Vector Table (IVT) mein uske handler ka seedha function pointer hota hai. Non-vectored mein CPU ko saare devices ko ek-ek karke poll karna padta hai.'

⚡ 1-Line Revision Rule:Interrupt = Asynchronous alert. DMA = Dedicated hardware coprocessor jo memory transfer khud sambhalta hai.

Layer 1: Intuition & Why It Matters

The Core Mental Model

“Programmed I/O is standing by the mailbox all day checking if a letter arrived. Interrupt-Driven I/O is sitting inside reading a book until the delivery driver rings your doorbell. DMA is hiring a personal assistant who receives 50 packages and stacks them directly in your garage without interrupting you at all.”

Why This Exists

When an SSD reads a 4K video at 7000 MB/s, if the CPU had to move every single byte through an accumulator register, your computer would freeze completely. DMA allows peripherals to copy data straight into RAM while the CPU keeps running your games and browsers.

Beginner Foundation

Your keyboard, mouse, screen, and hard drive are much slower than the CPU. The computer needs smart ways to talk to them without waiting for minutes. Interrupts and DMA let the CPU do important math while background chips handle the slow typing and printing.

Micro Concepts Decomposition

MICRO CONCEPT 1Canonical Object

Three Modes of I/O Data Transfer

1) Programmed I/O: CPU polls device busy flag continuously in a busy-wait loop (100% CPU waste). 2) Interrupt-Initiated I/O: CPU executes other tasks; device raises hardware interrupt when ready. 3) Direct Memory Access (DMA): Dedicated hardware chip transfers large data blocks between I/O and RAM with zero CPU intervention.

Key Takeaway: DMA provides the highest data transfer bandwidth, bypassing CPU cycles during block transfers.

MICRO CONCEPT 2Canonical Object

DMA Controller Operation: Burst vs Cycle Stealing Mode

In Burst Mode, the DMA controller takes complete control of the system bus and transfers an entire block before releasing it. In Cycle Stealing Mode, the DMA controller steals exactly one memory bus cycle per transfer from the CPU, interleaving transfers without freezing CPU execution.

Key Takeaway: Cycle stealing prevents CPU starvation during high-volume I/O operations.

MICRO CONCEPT 3Canonical Object

Interrupt Hardware, Priority & Vector Tables

When an interrupt occurs: 1) CPU finishes current instruction. 2) Saves PC and Flags on Stack. 3) Acknowledges with INTA signal. 4) Device places Interrupt Vector on data bus. 5) CPU jumps to Interrupt Service Routine (ISR) address found in Interrupt Vector Table (IVT).

Key Takeaway: Vectored interrupts allow hardware to branch directly to the specialized handler without software polling.

MICRO CONCEPT 4Canonical Object

8051 Microcontroller Architecture & Special Function Registers (SFRs)

The 8051 has 128 bytes internal RAM and 21 SFRs mapped at addresses 80H-FFH: Accumulator (ACC, E0H), B register (F0H), Program Status Word (PSW, D0H), Stack Pointer (SP, 81H), Data Pointer (DPTR, 82H-83H), Timer Mode (TMOD, 89H), Timer Control (TCON, 88H), and I/O Ports P0-P3.

Key Takeaway: 8051 SFRs control hardware peripherals (timers, serial UART, I/O pins, and interrupts) via memory-mapped byte and bit addresses.

Layer 3 & 4: Formal Specification & Mechanism

Hardware State Machine Architecture

DMA Handshake Protocol: 1. Peripheral requests data transfer via DREQ line to DMA Controller. 2. DMA Controller asserts HOLD (Bus Request) to CPU. 3. CPU finishes current machine cycle, places address/data buses in High-Impedance, and asserts HLDA (Hold Acknowledge). 4. DMA Controller asserts DACK to device, drives Memory Address, and activates MEMW and IOR lines. 5. Once Word Count register reaches 0, DMA controller asserts Interrupt TC (Terminal Count) and releases HOLD.

8051 Special Function Register Map (SFR 80H-FFH): - Accumulator (ACC, E0H): math and logic register. - B Register (F0H): used with ACC for MUL and DIV instructions. - PSW (D0H): Carry (CY), Auxiliary Carry (AC), Register Bank Select (RS1, RS0), Overflow (OV), Parity (P). - SP (81H): 8-bit Stack Pointer (initialized to 07H on reset). - DPTR (DPH 83H, DPL 82H): 16-bit register accessing external 64 KB RAM. - Ports P0 (80H), P1 (90H), P2 (A0H), P3 (B0H): 8-bit bi-directional I/O latches.

Layer 7: Interactive Laboratory

Interactive Simulator

COA • LABDirect Memory Access (DMA) & Cycle Stealing Laboratory

Launch Fullscreen Lab

COA • SYSTEM BUS & INTERCONNECTMulti-Master Bus Arbitration

Bus Arbitration Protocols & Priority Resolution Laboratory

Bus Master Devices (Click to Toggle Bus Request BR)Priority Order: Device 1 > Device 2 > Device 3

Master Device 1IDLE

Priority: Rank #1

Master Device 2BUS GRANTED

Priority: Rank #2

Master Device 3REQUESTING

Priority: Rank #3

Signal Wire Topology & Bus Controller State:DAISY CHAINING

[Bus Controller] ---BG Line---> [Device 1] ---BG Line---> [Device 2] ---BG Line---> [Device 3]

Common Bus Request Line (BR): HIGH (Asserted)

Bus Busy Line (BBSY): HIGH (Occupied by Device 2)

Engineering Tradeoffs:

Daisy Chaining: Lowest hardware cost (requires only 3 control lines regardless of master count). However, propagation delay is proportional to device count ($O(n)$), and any device failure in the chain breaks grant transmission down the line.

Layer 5: Step-by-Step Worked Numerical Example

End-to-End Execution Trace

Problem: Calculate the percentage of CPU time saved when switching from Programmed I/O to Interrupt-driven I/O for a hard drive transferring data at 1 MB/sec, where each character transfer takes 4 microseconds of CPU polling in programmed I/O, vs an ISR that takes 2 microseconds per interrupt. Solution: Characters/sec = 1,000,000. Programmed I/O CPU time = 1,000,000 * 4 us = 4,000,000 us = 4 seconds per second (CPU 100% pegged). Interrupt I/O with 1 KB buffer (1000 interrupts/sec) = 1000 * 2 us = 2000 us = 0.002 seconds = 0.2% CPU time. CPU overhead reduced by 99.8%!

Layer 6: Active Runtime CodeLab

Step-by-Step Code Execution (C)

AURXON Sandbox

AURXON Digital Engine

Font

main.cGlacier Light

Ln 1 • GCC 13

// C Emulation of DMA Controller Cycle Stealing Data Transfer
#include <stdio.h>
#include <stdbool.h>
 
typedef struct {
    int addressRegister;
    int wordCountRegister;
    bool terminalCount;
} DMAController;
 
void dmaTransferBlock(DMAController *dma, int ram[], int diskData[], int count) {
    dma->addressRegister = 0;
    dma->wordCountRegister = count;
    dma->terminalCount = false;
 
    printf("[DMA Controller] Acquiring bus via HOLD... Granted!\n");
    while (dma->wordCountRegister > 0) {
        // Cycle Stealing: Transfer 1 word straight to RAM
        ram[dma->addressRegister] = diskData[dma->addressRegister];
        dma->addressRegister++;
        dma->wordCountRegister--;
    }
    dma->terminalCount = true;
    printf("[DMA Controller] Transfer complete! Terminal Count reached. Releasing bus and raising interrupt to CPU.\n");
}
 
int main() {
    int ram[16] = {0};
    int diskData[4] = {0x11, 0x22, 0x33, 0x44};
    DMAController dma;
 
    dmaTransferBlock(&dma, ram, diskData, 4);
    for (int i = 0; i < 4; i++) {
        printf("RAM[%d] = 0x%X\n", i, ram[i]);
    }
    return 0;
}

// C Emulation of DMA Controller Cycle Stealing Data Transfer
#include <stdio.h>
#include <stdbool.h>

typedef struct {
    int addressRegister;
    int wordCountRegister;
    bool terminalCount;
} DMAController;

void dmaTransferBlock(DMAController *dma, int ram[], int diskData[], int count) {
    dma->addressRegister = 0;
    dma->wordCountRegister = count;
    dma->terminalCount = false;

printf("[DMA Controller] Acquiring bus via HOLD... Granted!\n");
    while (dma->wordCountRegister > 0) {
        // Cycle Stealing: Transfer 1 word straight to RAM
        ram[dma->addressRegister] = diskData[dma->addressRegister];
        dma->addressRegister++;
        dma->wordCountRegister--;
    }
    dma->terminalCount = true;
    printf("[DMA Controller] Transfer complete! Terminal Count reached. Releasing bus and raising interrupt to CPU.\n");
}

int main() {
    int ram[16] = {0};
    int diskData[4] = {0x11, 0x22, 0x33, 0x44};
    DMAController dma;

dmaTransferBlock(&dma, ram, diskData, 4);
    for (int i = 0; i < 4; i++) {
        printf("RAM[%d] = 0x%X\n", i, ram[i]);
    }
    return 0;
}

1115 chars • 38 lines • Ln 1UTF-8 • 4 Spaces

Interactive Terminal Shell

Sandbox Terminal Ready

Click Run Code or press Ctrl+Enter to compile and execute.

⚡ AURXON Bitstream Runtime v4.8IDRAS Academic Virtual Node

Common Student Pitfalls & Mistakes

Where Students Lose Marks

❌ Mistake: Assuming the 8051 Stack Pointer grows downwards like x86.

✓ Correct Understanding: In the 8051 microcontroller, the stack pointer increments on PUSH and decrements on POP (grows upwards towards higher RAM addresses).

Layer 8: Practice & Knowledge Verification

Active Assessment Quiz

No Practice Questions Configured

Questions for this topic are currently undergoing faculty review.

Academic Evaluation Preparation

Viva Examination & University Scoring Strategy

Standard Viva Examination Questions

Q1: What is the difference between Memory-Mapped I/O and Port-Mapped (Isolated) I/O?

Answer: Memory-Mapped I/O shares the same address space and instructions (MOV, LOAD, STORE) for both memory and I/O devices. Isolated I/O uses a separate address space and dedicated instructions (IN, OUT) with separate control lines (IOR, IOW).

How to Write High-Scoring University Exam Answers

Compare Programmed I/O, Interrupt-Driven I/O, and DMA with block diagrams and flowcharts. Detail the DMA controller architecture and describe the HOLD/HLDA bus master exchange. Sketch the 8051 Microcontroller block diagram and describe PSW, DPTR, and Timer SFRs.